Memory devices are used as storage for digital data in a lot of electronic integrated circuits (ICs), for example in computers, processors, microcontrollers etc. One basic type of a memory device is Random Access Memory (RAM) which is of two types: static RAM (SRAM) and dynamic RAM (DRAM). In a SRAM memory an array of cells is used to store data and each cell can store one bit of data i.e. “0” or “1”. A typical SRAM consists of a pair of cross-coupled inverters which form a latch to store the data. Data to be written into this cell is driven from the bit lines which are connected to these cross-coupled inverters via pass gates which are typically N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices (NMOS).
For a successful write operation, the data on the bitlines should be strong enough to overpower the cross-coupled inverter latch to write the new data on the cell. In part because of their uses in biomedical and Internet-of-Things (IOT) applications, the supply voltage of such devices has been scaled down. As a direct result of this scaling down of the supply voltage, the writeability of the SRAM cell has deteriorated. As the technology is shrinking there are significant concerns about power dissipation and leakage of memory devices as well.
Various methods of implement write assist (WA) circuits have been proposed to improve the write performance of SRAM cells. The most widely used method is the negative bitline write assist technique. In this technique, the bitline through which “0” is being written is driven below the reference ground voltage to strengthen the pass gates by increasing its source-gate voltage.
In the prior art technique, a negative voltage bump is generated on the bitline by using coupling capacitor. The bump is directly proportional to the size of capacitor and supply voltage. To achieve successful low voltage write operation a large capacitor is required. However, using a large capacitor means a larger negative bump at higher supply voltages, when no negative bump is needed. Having the larger negative bump a causes severe reliability and aging issue to the SRAM cell. This overstressing may lead to oxide breakdown of the NMOS pass gate and cause a loss of yield of SRAM cell. The reliability concern has a huge impact on fabrication costs as well as the lifespan of the memory device and consequently the whole electronic system on chip (SoC). Also, a large negative bump can create data retention issues in unselected SRAM cells where pass gates can be turned on due to increased gale-source voltage. These issues are especially apparent when the SRAM cell operates in ultra-low voltage applications (IoT, wireless and biomedical application).